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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Stack register</span></span>
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</style><div role="note" class="hatnote navigation-not-searchable">For broader coverage of stack pointers, see <a href="Stack_(abstract_data_type)#Basic_architecture_of_a_stack" title="Stack (abstract data type)">Stack (abstract data type) § Basic architecture of a stack</a>, and <a href="Call_stack#Structure" title="Call stack">Call stack § Structure</a>.</div>
<p>A <b>stack register</b> is a computer central <a href="Processor_register" title="Processor register">processor register</a> whose purpose is to keep track of a <a href="Call_stack" title="Call stack">call stack</a>. On an <a href="Accumulator-based_architecture" class="mw-redirect" title="Accumulator-based architecture">accumulator-based architecture</a> machine, this may be a dedicated register. On a machine with multiple <a href="General-purpose_registers" class="mw-redirect" title="General-purpose registers">general-purpose registers</a>, it may be a register that is reserved by convention, such as on the <a href="IBM_System/360" title="IBM System/360">IBM System/360</a> through <a href="Z/Architecture" title="Z/Architecture">z/Architecture</a> architecture and <a href="RISC" class="mw-redirect" title="RISC">RISC</a> architectures, or it may be a register that procedure call and return instructions are hardwired to use, such as on the <a href="PDP-11" title="PDP-11">PDP-11</a>, <a href="VAX" title="VAX">VAX</a>, and <a href="Intel_x86" class="mw-redirect" title="Intel x86">Intel x86</a> architectures. Some designs such as the <a href="Data_General_Eclipse" title="Data General Eclipse">Data General Eclipse</a> had no dedicated register, but used a reserved hardware memory address for this function.
</p><p>Machines before the late 1960s—such as the <a href="PDP-8" title="PDP-8">PDP-8</a> and <a href="HP_2100" title="HP 2100">HP 2100</a>—did not have compilers which supported <a href="Recursion_(computer_science)" title="Recursion (computer science)">recursion</a>. Their subroutine instructions typically would save the current location in the jump address, and then set the program counter to the <i>next</i> address.<sup id="cite_ref-Salomon_1993_1-0" class="reference"><a href="#cite_note-Salomon_1993-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> While this is simpler than maintaining a stack, since there is only one return location per subroutine code section, there cannot be recursion without considerable effort on the part of the programmer.
</p><p>A <a href="Stack_machine" title="Stack machine">stack machine</a> may have 2 or more stack registers — one of them keeps track of a <a href="Call_stack" title="Call stack">call stack</a>, the other(s) keep track of other <a href="Stack_(data_structure)" class="mw-redirect" title="Stack (data structure)">stack</a>(s).
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<div class="mw-heading mw-heading2"><h2 id="Stack_registers_in_x86">Stack registers in x86</h2></div>
<p>In the 16-bit version of the <a href="X86" title="X86">x86</a> architecture, the main stack register is the 16-bit <b>Stack Pointer</b> (SP), with the 32-bit <a href="IA-32" title="IA-32">IA-32</a> version extending SP to the 32-bit <b>Extended Stack Pointer</b> (ESP), and the 64-bit <a href="X86-64" title="X86-64">x86-64</a> version extending ESP to the 64-bit <b>Register Stack Pointer</b> (RSP). The stack segment register (SS) is usually used to store information about the <a href="Memory_segment" class="mw-redirect" title="Memory segment">memory segment</a> that stores the <a href="Call_stack" title="Call stack">call stack</a> of currently executed program. SP points to current stack top. By default, the stack grows downward in memory, so newer values are placed at lower memory addresses. To save a value to the stack, the <code>PUSH</code> instruction is used. To retrieve a value from the stack, the <code>POP</code> instruction is used.
</p><p><b>Example</b>: Assuming that SS = 1000h and SP = 0xF820. This means that current stack top is the physical address 0x1F820 (this is due to <a href="Intel_8086#Segmentation" title="Intel 8086">memory segmentation in 8086</a>). The next two machine instructions of the program are:
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<div class="mw-highlight mw-highlight-lang-asm mw-content-ltr" dir="ltr"><pre><span class="nf">PUSH</span><span class="w"> </span><span class="no">AX</span>
<span class="nf">PUSH</span><span class="w"> </span><span class="no">BX</span>
</pre></div>
<ul><li>These first instruction shall push the value stored in AX (16-bit register) to the stack. This is done by subtracting a value of 2 (2 bytes) from SP.</li>
<li>The new value of SP becomes 0xF81E. The CPU then copies the value of AX to the memory word whose physical address is 0x1F81E.</li>
<li>When "PUSH BX" is executed, SP is set to 0xF81C and BX is copied to 0x1F81C.<sup id="cite_ref-Howard_2013_2-0" class="reference"><a href="#cite_note-Howard_2013-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></li></ul>
<p>This illustrates how PUSH works. Usually, the running program pushes registers to the stack to make use of the registers for other purposes, like to call a routine that may change the current values of registers. To restore the values stored at the stack, the program shall contain machine instructions like this:
</p>
<div class="mw-highlight mw-highlight-lang-asm mw-content-ltr" dir="ltr"><pre><span class="nf">POP</span><span class="w"> </span><span class="no">BX</span>
<span class="nf">POP</span><span class="w"> </span><span class="no">AX</span>
</pre></div>
<ul><li><code>POP BX</code> copies the word at 0x1F81C (which is the old value of BX) to BX, then increases SP by 2. SP now is 0xF81E.</li>
<li><code>POP AX</code> copies the word at 0x1F81E to AX, then sets SP to 0xF820.<sup id="cite_ref-NB1_3-0" class="reference"><a href="#cite_note-NB1-3"><span class="cite-bracket">[</span>nb 1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-NB2_4-0" class="reference"><a href="#cite_note-NB2-4"><span class="cite-bracket">[</span>nb 2<span class="cite-bracket">]</span></a></sup></li></ul>
<div class="mw-heading mw-heading2"><h2 id="Stack_engine">Stack engine</h2></div>
<p>Simpler processors store the stack pointer in a regular <a href="Hardware_register" title="Hardware register">hardware register</a> and use the <a href="Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic unit</a> (ALU) to manipulate its value. Typically push and pop are translated into multiple <a href="Micro-op" class="mw-redirect" title="Micro-op">micro-ops</a>, to separately add/subtract the stack pointer, and perform the load/store in memory.<sup id="cite_ref-Stokes_2004_5-0" class="reference"><a href="#cite_note-Stokes_2004-5"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>
</p><p>Newer processors contain a dedicated <b>stack engine</b> to optimize stack operations. <a href="Pentium_M" title="Pentium M">Pentium M</a> was the first x86 processor to introduce a stack engine. In its implementation, the stack pointer is split among two registers: ESP<sub>O</sub>, which is a 32-bit register, and ESP<sub>d</sub>, an 8-bit delta value that is updated directly by stack operations. PUSH, POP, CALL and RET opcodes operate directly with the ESP<sub>d</sub> register. If ESP<sub>d</sub> is near overflow or the ESP register is referenced from other instructions (when ESP<sub>d</sub> ≠ 0), a synchronisation micro-op is inserted that updates the ESP<sub>O</sub> using the ALU and resets ESP<sub>d</sub> to 0. This design has remained largely unmodified in later Intel processors, although ESP<sub>O</sub> has been expanded to 64 bits.<sup id="cite_ref-Fog_6-0" class="reference"><a href="#cite_note-Fog-6"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>
</p><p>A stack engine similar to Intel's was also adopted in the <a href="AMD_K8" title="AMD K8">AMD K8</a> microarchitecture. In <a href="Bulldozer_(microarchitecture)" title="Bulldozer (microarchitecture)">Bulldozer</a>, the need for synchronization micro-ops was removed, but the internal design of the stack engine is not known.<sup id="cite_ref-Fog_6-1" class="reference"><a href="#cite_note-Fog-6"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>
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<div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2></div>
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<li id="cite_note-NB1-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-NB1_3-0">^</a></b></span> <span class="reference-text">The program above pops BX first because it was pushed last.</span>
</li>
<li id="cite_note-NB2-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-NB2_4-0">^</a></b></span> <span class="reference-text">In 8086, <code>PUSH</code> & <code>POP</code> instructions can only work with 16-bit elements.</span>
</li>
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<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>
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<li id="cite_note-Salomon_1993-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-Salomon_1993_1-0">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">
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</style><cite id="CITEREFSalomon1993" class="citation book cs1 cs1-prop-location-test">Salomon, David (February 1993) [1992]. Written at California State University, Northridge, California, USA. Chivers, Ian D. (ed.). <a rel="nofollow" class="external text" href="http://www.davidsalomon.name/assem.advertis/asl.pdf"><i>Assemblers and Loaders</i></a> <span class="cs1-format">(PDF)</span>. Ellis Horwood Series In Computers And Their Applications (1 ed.). Chicester, West Sussex, UK: <a href="Ellis_Horwood_Limited" class="mw-redirect" title="Ellis Horwood Limited">Ellis Horwood Limited</a> / <a href="Simon_%26_Schuster_International_Group" class="mw-redirect" title="Simon & Schuster International Group">Simon & Schuster International Group</a>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-13-052564-2</bdi>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200323010358/http://www.davidsalomon.name/assem.advertis/asl.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2020-03-23<span class="reference-accessdate">. Retrieved <span class="nowrap">2008-10-01</span></span>. <q>Most computers save the return address in either the stack, in one of the registers, or in the first word of the procedure (in which case the first executable instruction of the procedure should be stored in the second word). If the latter method is used, a return from the procedure is a jump to the memory location whose address is contained in the first word of the procedure.</q></cite> (xiv+294+4 pages)</span>
</li>
<li id="cite_note-Howard_2013-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-Howard_2013_2-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFHoward" class="citation web cs1">Howard, Brian. <a rel="nofollow" class="external text" href="http://www.csc.depauw.edu/~bhoward/asmtut/asmtut4.html">"Assembly Tutorial - Instructions"</a>. <i>Computer Science Department, DePauw University</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2013-07-19</span></span>.</cite></span>
</li>
<li id="cite_note-Stokes_2004-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-Stokes_2004_5-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFStokes2004" class="citation web cs1">Stokes, Jon "Hannibal" (2004-02-25). <a rel="nofollow" class="external text" href="http://archive.arstechnica.com/cpu/004/pentium-m/m-pentium-m-5.html">"A Look at Centrino's Core: The Pentium M"</a>. <i>archive.arstechnica.com</i>. p. 5.</cite></span>
</li>
<li id="cite_note-Fog-6"><span class="mw-cite-backlink">^ <a href="#cite_ref-Fog_6-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Fog_6-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFFog" class="citation web cs1">Fog, Agner. <a rel="nofollow" class="external text" href="http://www.agner.org/optimize/microarchitecture.pdf">"The microarchitecture of Intel, AMD and VIA CPUs"</a> <span class="cs1-format">(PDF)</span>. Technical University of Denmark.</cite></span>
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</style><div id="Processor_technologies439" style="font-size:114%;margin:0 4em"><a href="Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Abstract_machine" title="Abstract machine">Abstract machine</a></li>
<li><a href="Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li>
<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>
<ul><li><a href="Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li>
<li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li>
<li><a href="Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li>
<li><a href="Queue_automaton" title="Queue automaton">Queue automaton</a></li>
<li><a href="Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li>
<li><a href="Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li>
<li><a href="Turing_machine" title="Turing machine">Turing machine</a>
<ul><li><a href="Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li>
<li><a href="Universal_Turing_machine" title="Universal Turing machine">Universal</a></li>
<li><a href="Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li>
<li><a href="Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li>
<li><a href="Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li>
<li><a href="Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li>
<li><a href="Hypercomputation" title="Hypercomputation">Hypercomputation</a></li>
<li><a href="Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li>
<li><a href="History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li>
<li><a href="Stack_machine" title="Stack machine">Stack machine</a></li>
<li><a href="Register_machine" title="Register machine">Register machines</a>
<ul><li><a href="Counter_machine" title="Counter machine">Counter</a></li>
<li><a href="Pointer_machine" title="Pointer machine">Pointer</a></li>
<li><a href="Random-access_machine" title="Random-access machine">Random-access</a></li>
<li><a href="Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></li>
<li><a href="Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li>
<li><a href="Harvard_architecture" title="Harvard architecture">Harvard</a>
<ul><li><a href="Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li>
<li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>
<li><a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li>
<li><a href="Cellular_architecture" title="Cellular architecture">Cellular</a></li>
<li><a href="Endianness" title="Endianness">Endianness</a></li>
<li><a href="Computer_data_storage" title="Computer data storage">Memory access</a>
<ul><li><a href="Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li>
<li><a href="Uniform_memory_access" title="Uniform memory access">HUMA</a></li>
<li><a href="Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li>
<li><a href="Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li>
<li><a href="Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li>
<li><a href="Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a>
<ul><li><a href="Virtual_memory" title="Virtual memory">Virtual memory</a></li>
<li><a href="Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li>
<li><a href="Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li>
<li><a href="Fabric_computing" title="Fabric computing">Fabric</a></li>
<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>
<li><a href="Cognitive_computing" title="Cognitive computing">Cognitive</a></li>
<li><a href="Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set<br>architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li>
<li><a href="Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li>
<li><a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li>
<li><a href="Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li>
<li><a href="Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a>
<ul><li><a href="TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li>
<li><a href="Very_long_instruction_word" title="Very long instruction word">VLIW</a>
<ul><li><a href="Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li>
<li><a href="Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li>
<li><a href="One-instruction_set_computer" title="One-instruction set computer">OISC</a></li>
<li><a href="No_instruction_set_computing" title="No instruction set computing">NISC</a></li>
<li><a href="Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li>
<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>
<li><a href="Quantum_computing" title="Quantum computing">Quantum computing</a></li>
<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a>
<ul><li><a href="Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br>sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li>
<li><a href="VAX" title="VAX">VAX</a></li>
<li><a href="PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li>
<li><a href="X86" title="X86">x86</a></li>
<li><a href="ARM_architecture_family" title="ARM architecture family">ARM</a></li>
<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li>
<li><a href="MIPS_architecture" title="MIPS architecture">MIPS</a></li>
<li><a href="MIPS-X" title="MIPS-X">MIPS-X</a></li>
<li>Power
<ul><li><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li>
<li><a href="PowerPC" title="PowerPC">PowerPC</a></li>
<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li></ul></li>
<li><a href="Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li>
<li><a href="SPARC" title="SPARC">SPARC</a></li>
<li><a href="SuperH" title="SuperH">SuperH</a></li>
<li><a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li>
<li><a href="ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li>
<li><a href="M32R" title="M32R">M32R</a></li>
<li><a href="Unicore" title="Unicore">Unicore</a></li>
<li><a href="IA-64" title="IA-64">Itanium</a></li>
<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a></li>
<li><a href="RISC-V" title="RISC-V">RISC-V</a></li>
<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>
<li><a href="Little_man_computer" class="mw-redirect" title="Little man computer">LMC</a></li>
<li>System/3x0
<ul><li><a href="IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li>
<li><a href="IBM_System/370" title="IBM System/370">S/370</a></li>
<li><a href="IBM_System/390" title="IBM System/390">S/390</a></li>
<li><a href="Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li>
<li>Tilera ISA</li>
<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>
<li><a href="Adapteva" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li>
<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li>
<li><a href="Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li>
<li><a href="Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Data_dependency" title="Data dependency">Data dependency</a></li>
<li><a href="Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li>
<li><a href="Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li>
<li><a href="False_sharing" title="False sharing">False sharing</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Scoreboarding" title="Scoreboarding">Scoreboarding</a></li>
<li><a href="Tomasulo's_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a>
<ul><li><a href="Reservation_station" title="Reservation station">Reservation station</a></li>
<li><a href="Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li>
<li><a href="Register_renaming" title="Register renaming">Register renaming</a></li>
<li><a href="Wide-issue" title="Wide-issue">Wide-issue</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Branch_predictor" title="Branch predictor">Branch prediction</a></li>
<li><a href="Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Bit-level_parallelism" title="Bit-level parallelism">Bit</a>
<ul><li><a href="Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li>
<li><a href="Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li>
<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>
<li><a href="Instruction_pipelining" title="Instruction pipelining">Pipelining</a>
<ul><li><a href="Scalar_processor" title="Scalar processor">Scalar</a></li>
<li><a href="Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li>
<li><a href="Task_parallelism" title="Task parallelism">Task</a>
<ul><li><a href="Thread_(computing)" title="Thread (computing)">Thread</a></li>
<li><a href="Process_(computing)" title="Process (computing)">Process</a></li></ul></li>
<li><a href="Data_parallelism" title="Data parallelism">Data</a>
<ul><li><a href="Vector_processor" title="Vector processor">Vector</a></li></ul></li>
<li><a href="Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>
<li><a href="Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>
<li><a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a>
<ul><li><a href="Hyper-threading" title="Hyper-threading">Hyperthreading</a></li>
<li><a href="Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li>
<li><a href="Speculative_multithreading" title="Speculative multithreading">Speculative</a></li>
<li><a href="Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>
<li><a href="Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Single_instruction%2C_single_data" title="Single instruction, single data">SISD</a></li>
<li><a href="Single_instruction%2C_multiple_data" title="Single instruction, multiple data">SIMD</a>
<ul><li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li>
<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li>
<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li>
<li><a href="SWAR" title="SWAR">SWAR</a></li></ul></li>
<li><a href="Multiple_instruction%2C_single_data" title="Multiple instruction, single data">MISD</a></li>
<li><a href="Multiple_instruction%2C_multiple_data" title="Multiple instruction, multiple data">MIMD</a>
<ul><li><a href="Single_program%2C_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_performance" title="Computer performance">Processor<br>performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Transistor_count" title="Transistor count">Transistor count</a></li>
<li><a href="Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC)
<ul><li><a href="Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li>
<li><a href="Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li>
<li><a href="FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li>
<li><a href="Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li>
<li><a href="SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li>
<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li>
<li><a href="Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li>
<li><a href="Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li>
<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)
<ul><li>GPGPU</li></ul></li>
<li><a href="Vector_processor" title="Vector processor">Vector</a></li>
<li><a href="Barrel_processor" title="Barrel processor">Barrel</a></li>
<li><a href="Stream_processing" title="Stream processing">Stream</a></li>
<li><a href="Tile_processor" title="Tile processor">Tile processor</a></li>
<li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>
<li><a href="Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li>
<li><a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li>
<li><a href="Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li>
<li><a href="Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li>
<li><a href="Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li>
<li><a href="Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li>
<li><a href="System_in_a_package" title="System in a package">System in a package</a> (SiP)</li>
<li><a href="Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul>
</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Embedded_system" title="Embedded system">Embedded system</a></li>
<li><a href="Microprocessor" title="Microprocessor">Microprocessor</a></li>
<li><a href="Microcontroller" title="Microcontroller">Microcontroller</a></li>
<li><a href="Mobile_processor" title="Mobile processor">Mobile</a></li>
<li><a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li>
<li><a href="Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li>
<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br>on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li>
<li><a href="Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li>
<li><a href="Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li>
<li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_acceleration" title="Hardware acceleration">Hardware<br>accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>
<li><a href="AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerator</a></li>
<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li>
<li><a href="Image_processor" title="Image processor">Image processor</a></li>
<li><a href="Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li>
<li><a href="Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li>
<li><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li>
<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li>
<li><a href="Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li>
<li><a href="Network_processor" title="Network processor">Network processor</a></li>
<li><a href="Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul>
</div></td></tr></tbody></table><div>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="1-bit_computing" title="1-bit computing">1-bit</a></li>
<li><a href="4-bit_computing" title="4-bit computing">4-bit</a></li>
<li><a href="8-bit_computing" title="8-bit computing">8-bit</a></li>
<li><a href="12-bit_computing" title="12-bit computing">12-bit</a></li>
<li><a href="Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li>
<li><a href="16-bit_computing" title="16-bit computing">16-bit</a></li>
<li><a href="24-bit_computing" title="24-bit computing">24-bit</a></li>
<li><a href="32-bit_computing" title="32-bit computing">32-bit</a></li>
<li><a href="48-bit_computing" title="48-bit computing">48-bit</a></li>
<li><a href="64-bit_computing" title="64-bit computing">64-bit</a></li>
<li><a href="128-bit_computing" title="128-bit computing">128-bit</a></li>
<li><a href="256-bit_computing" title="256-bit computing">256-bit</a></li>
<li><a href="512-bit_computing" title="512-bit computing">512-bit</a></li>
<li><a href="Bit_slicing" title="Bit slicing">bit slicing</a></li>
<li><a href="Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a>
<ul><li><a href="Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Single-core" title="Single-core">Single-core</a></li>
<li><a href="Multi-core_processor" title="Multi-core processor">Multi-core</a></li>
<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>
<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Central_processing_unit" title="Central processing unit">Core</a></li>
<li><a href="Cache_(computing)" title="Cache (computing)">Cache</a>
<ul><li><a href="CPU_cache" title="CPU cache">CPU cache</a></li>
<li><a href="Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li>
<li><a href="Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li>
<li><a href="Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li>
<li><a href="Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li>
<li><a href="Cache_coherence" title="Cache coherence">coherence</a></li></ul></li>
<li><a href="Bus_(computing)" title="Bus (computing)">Bus</a></li>
<li><a href="Clock_rate" title="Clock rate">Clock rate</a></li>
<li><a href="Clock_signal" title="Clock signal">Clock signal</a></li>
<li><a href="FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul>
</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Execution_unit" title="Execution unit">Functional<br>units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li>
<li><a href="Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li>
<li><a href="Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li>
<li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU)
<ul><li><a href="Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li>
<li><a href="Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li>
<li><a href="Branch_predictor" title="Branch predictor">Branch predictor</a></li>
<li><a href="Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li>
<li><a href="Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC)
<ul><li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li>
<li><a href="Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Combinational_logic" title="Combinational logic">Combinational</a></li>
<li><a href="Sequential_logic" title="Sequential logic">Sequential</a></li>
<li><a href="Glue_logic" title="Glue logic">Glue</a></li>
<li><a href="Logic_gate" title="Logic gate">Logic gate</a>
<ul><li><a href="Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li>
<li><a href="Gate_array" title="Gate array">Array</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Processor_register" title="Processor register">Processor register</a></li>
<li><a href="Status_register" title="Status register">Status register</a></li>
<li><a href="Register_file" title="Register file">Register file</a></li>
<li><a href="Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li>
<li><a href="Memory_address_register" title="Memory address register">Memory address register</a></li>
<li><a href="Program_counter" title="Program counter">Program counter</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li>
<li><a href="Instruction_unit" title="Instruction unit">Instruction unit</a></li>
<li><a href="Data_buffer" title="Data buffer">Data buffer</a></li>
<li><a href="Write_buffer" title="Write buffer">Write buffer</a></li>
<li><a href="Microcode" title="Microcode">Microcode</a> <a href="ROM_image" title="ROM image">ROM</a></li>
<li><a href="Counter_(digital)" title="Counter (digital)">Counter</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Multiplexer" title="Multiplexer">Multiplexer</a></li>
<li><a href="Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li>
<li><a href="Adder_(electronics)" title="Adder (electronics)">Adder</a></li>
<li><a href="Binary_multiplier" title="Binary multiplier">Multiplier</a>
<ul><li><a href="CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li>
<li><a href="Binary_decoder" title="Binary decoder">Binary decoder</a>
<ul><li><a href="Address_decoder" title="Address decoder">Address decoder</a></li>
<li><a href="Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li>
<li><a href="Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a>
<ul><li><a href="Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li>
<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li>
<li><a href="Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li>
<li><a href="Boolean_circuit" title="Boolean circuit">Boolean</a></li>
<li><a href="Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li>
<li><a href="Analogue_electronics" title="Analogue electronics">Analog</a></li>
<li><a href="Quantum_circuit" title="Quantum circuit">Quantum</a></li>
<li><a href="Switch#Electronic_switches" title="Switch">Switch</a></li></ul>
</div></td></tr></tbody></table><div>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Power_management" title="Power management">Power<br>management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Power_Management_Unit" title="Power Management Unit">PMU</a></li>
<li><a href="Advanced_Power_Management" title="Advanced Power Management">APM</a></li>
<li><a href="ACPI" title="ACPI">ACPI</a></li>
<li><a href="Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li>
<li><a href="Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li>
<li><a href="Clock_gating" title="Clock gating">Clock gating</a></li>
<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li>
<li><a href="Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li>
<li><a href="Processor_design" title="Processor design">Processor design</a></li>
<li><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></li>
<li><a href="Hardware_security_module" title="Hardware security module">Hardware security module</a></li>
<li><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li>
<li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>
<li><a href="Pin_grid_array" title="Pin grid array">Pin grid array</a></li>
<li><a href="Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul>
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